A split-rail SRAM includes two power supplies namely periphery supply voltage (VDDPR) and array supply voltage (VDDAR) and these supply voltages may vary in an uncorrelated manner which impacts a delay of a tracking circuit responsible for generating sense enable (SE) signal. The tracking circuit tracks the delay required for generating SE signal when minimum sufficient voltage is established across bit lines. If SE signal is generated before the minimum sufficient voltage developed, there are chances of a READ operation failure.
A conventional tracking circuit 100 is illustrated in FIG. 1. The tracking circuit 100 includes two dummy cells which models column parasitic resistance and capacitance (RC) (dummy column 125) and row parasitic RC (dummy row 130) to track the rows and column discharge delay across voltage corners. Initially, point A 107 is pulled high and with the clock going high and point B 109 is pulled low using an internal signal generated from clock generator 135. With point B going low, the parasitic capacitance starts to discharge imitating fraction of discharge time the actual bit line takes to discharge.
The rate of discharge current is controlled by two parallel paths using NMOS transistor 105 and NMOS transistors 110, 115 which decides the discharge current through each path. The gates of these NMOS transistors 110, 115 are connected to one of the supply voltages, VDDAR and VDDPR. Depending on the supply voltage value, the rate of discharge varies which in turn decides the time for generating SE signal 140. When a discharge path is tuned to one voltage corner, it either results in considerable power and performance loss and acceleration of SE signal generation in the other voltage corner. In the latter case, SE signal is generated before a sufficient minimum differential voltage is established across bit lines which is required by sense amplifier to correctly sense and resolve to digital output. This increases the possibility of READ failure.